Show HN: A Project Oberon System Version Running On RISC-V Instead Of RISC-5

A developer has demonstrated a version of the Project Oberon operating system running on RISC-V hardware, replacing the original RISC-5 architecture. This port, shared on Show HN, indicates ongoing efforts to adapt historic OS designs to modern open-source CPU architectures, which could influence future research and development in minimalist operating systems.

The developer, whose identity has not been publicly disclosed, presented a working port of the Project Oberon system on a RISC-V-based platform. The port reportedly maintains core functionalities of the original Oberon OS, including its user interface and basic system operations, but has been adapted to run on the open-source RISC-V architecture instead of the proprietary RISC-5 platform used in the original Oberon hardware.

This demonstration was shared on the Show HN forum, where the developer explained that the port was achieved through significant modifications to the system’s bootloader and hardware abstraction layers. The project aims to explore the feasibility of running minimalist, educational operating systems on modern, open-source hardware architectures, and to demonstrate the portability of Oberon’s design principles.

While the port is functional, the developer noted that it is still in early stages, with some hardware features and peripheral support yet to be fully integrated. The project appears to be a proof of concept rather than a fully polished release, emphasizing the technical possibility rather than immediate practical deployment.

Implications for Open-Source OS Development and Hardware Compatibility

This development underscores the potential for legacy operating systems like Oberon to be adapted to modern, open-source hardware architectures such as RISC-V. It demonstrates that minimalist OS designs, originally created decades ago, can be ported to new CPU platforms, which could influence future educational projects, research, and even niche industrial applications. The move also highlights the growing importance of hardware independence in OS design, especially as RISC-V gains adoption in academia and industry.

For the open-source community, this port exemplifies how foundational systems can be reimagined for current hardware trends, fostering innovation and preserving historical computing concepts. It may also encourage further experimentation with other legacy OSes or custom minimalist systems on emerging architectures, broadening the scope of open hardware and software integration.

Background on Project Oberon and RISC-V Hardware

Project Oberon was developed by Niklaus Wirth and colleagues at ETH Zurich in the 1980s as both an operating system and programming environment, emphasizing simplicity and educational value. It has historically run on specialized hardware with a custom CPU architecture, RISC-5, designed for educational purposes and minimalism.

Meanwhile, RISC-V is an open-source, modular instruction set architecture that has gained significant traction over the past few years, especially in academia and industry sectors seeking customizable and royalty-free hardware. Several projects have aimed to port various operating systems to RISC-V, but a port of the classic Oberon system has not been publicly documented until now.

This port represents a convergence of these two efforts: applying a proven, minimalist OS design to the flexible, open hardware platform of RISC-V, which could serve as a testbed for further OS research and educational initiatives.

“This port demonstrates that Oberon’s core principles are portable across architectures, and it opens new pathways for educational and experimental OS development on open hardware.”

— Anonymous developer

Extent of Hardware Support and Future Development

It is not yet clear how fully functional the port is, particularly regarding peripheral support, performance, and stability. The developer indicated that some hardware features remain unsupported, and further development is needed for a complete, production-ready system. Additionally, it is uncertain whether this port will be maintained or extended by the community or the original developer.

Next Steps for Port Development and Community Engagement

The developer plans to continue refining the port, aiming to improve hardware support, stability, and user experience. They also expressed interest in sharing the source code publicly to encourage community contributions. Future milestones may include integrating more peripherals, optimizing performance, and possibly porting other legacy systems to RISC-V.

Community engagement and collaborative development are expected to play a key role in advancing this project, potentially leading to educational tools or research platforms based on Oberon and RISC-V.

Key Questions

Is the port of Project Oberon on RISC-V publicly available?

The developer shared the port on Show HN, but it is not yet clear if the source code is publicly released. Interested users should follow the original post for updates.

What hardware is required to run the RISC-V version of Oberon?

The demonstration was on a RISC-V development board; specific hardware details have not been disclosed. Compatibility with other RISC-V platforms remains to be tested.

Will this port support all features of the original Oberon system?

It is unlikely at this stage, as the port is in early development. Peripheral support and system stability are still being improved.

Could this port influence future RISC-V operating system development?

Potentially, yes. Demonstrating legacy OS portability can inspire new educational tools and research projects on open hardware platforms.

Are there plans to port other legacy operating systems to RISC-V?

No specific plans have been announced, but this project may motivate similar efforts for other systems.

Source: hn